The present invention relates to a nonvolatile semiconductor storage device constructed of memory cells each including two nonvolatile memory elements which are controlled by one word gate and two control gates.
Known as a nonvolatile semiconductor device is the MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor or -Substrate) type wherein the gate insulator layer between a channel and a gate is formed of a stacked structure consisting of a silicon oxide film, a silicon nitride film and a silicon oxide film, and wherein electric charges are trapped in the silicon nitride film.
The MONOS type nonvolatile semiconductor storage device is disclosed in a publication, Y. Hayashi, et al.: 2000 Symposium on VLSI Technology, Digest of Technical Papers, p.122 to p.123. The publication teaches a MONOS flash memory cell including two nonvolatile memory elements (also termed “MONOS memory elements or cells”) which are controlled by one word gate and two control gates. That is, one flash memory cell has two trap sites for charges.
A plurality of MONOS flash memory cells each having such a structure are arranged in each of a row direction and a column direction, thereby to construct a memory cell array region.
Two bit lines, one word line and two control gate lines are required for driving the MONOS flash memory cell. In driving a large number of memory cells, however, such lines can be connected in common in a case where even the different control gates are set at the same potential.
The operations of the flash memory of this type include erasing, programming and reading data. Usually, each of the operations of programming and reading data is performed simultaneously in selected cells (selected nonvolatile memory elements) of 8 bits or 16 bits.
Here in the MONOS flash memory, a plurality of MONOS flash memory cells which are not isolated from one another are connected to one word line. Accordingly, not only the voltages of the MONOS flash memory cell having a certain specified selected cell, but also those of the MONOS flash memory cells adjacent thereto must be appropriately set in order to program data in the selected cell.
In this regard, the disturbance of data poses a problem in the nonvolatile memory of this type. The “disturbance of data” signifies a phenomenon in which, when data is programmed or erased by applying high potentials to the control gate line and bit line of the selected cell, the high potentials are also applied to an unselected cell (unselected nonvolatile memory element) by the shared wiring lines, and such a state is repeated every programming or erasing operation, whereby the unselected cell is programmed or erased, so that the data of the unselected cell is disturbed.
In order to avoid such a situation, each control gate line can be furnished with a selection gate circuit so as to apply the high potential only to the cell within a selected sector, and to prevent the high potential from being applied to the cell within an unselected sector.
With this contrivance, however, an area is occupied due to the selection gate circuits, and a high density of integration of memory cells is hampered. Further, when a voltage drop arises in the selection gate circuit, the component of the voltage drop needs to be fed in superposition in order to feed the high potential to the cell of the selected sector in the program mode. In consequence, the low voltage drive of the storage device is hampered, and the contrivance is unsuited to an equipment of which a low power consumption is required, especially a portable equipment.
Besides, even when the high potential is applied within only the selected sector as stated above, it is also applied to the unselected cell within the selected sector, and the disturbance in the unselected cell within the selected sector is unavoidable especially in the data erase mode.